the case statement part in verilog did't work -


i want design vending machine nt15 cola,my code below.

let deleted "case" statement part figure a. undeleted "case" statement part figure b. find 2 figures same,so wonder "case" statement part did't work.i can't understand why.is programm problem?can tell me why?plz

       `timescale 1ns/1ns       module vendor (nt5,nt10,clk,reset,cola,change);       input nt5 , nt10 , clk , reset;       output  reg  cola , change;       reg [1:0]five = 2'b00;       reg [1:0]ten = 2'b00;       reg [2:0] payment_state, next_state;       parameter d_0 = 3'b000,//0 dollar       d_5 = 3'b001,//5 dollar       ...                @(posedge clk )        begin            if(reset==1||cola==1)          begin           cola<=0;           change<=0;           five<=0;           ten<=0;               end        case (payment_state)         d_0 : begin               cola <= 0;             change <= 0;             if (five == 1'b1)                     next_state = d_5;              if (ten == 1'b1)                      next_state = d_10;             end         d_5 :  ...             d_10 : ...         d_15 : begin                    cola <= 1;                   change = 0;                   next_state = d_0;                 end            d_20 : begin                    cola <= 1;                   change = 1;                   next_state = d_0;                 end       default : begin                       next_state = d_0;                   cola<= 1;                   change<= 1;                end   endcase       if(nt5==1'b1)    begin    five<=five+1'b1;    end   if(nt10==1'b1)    begin        ten<=ten+1'b1;    end    end      endmodule

i think should test module under testbench first.

i think fsm not 1 or 2 or 3 block style.

i think article can you. coding , scripting techniques fsm designs synthesis-optimized, glitch-free outputs


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