VHDL: Division with error coding but there are errors in compiling on Quartus II but not on Xilinx ISE -

i'm new vhdl , help. see, told our instructor code division of binary (by converting binary integer first) , if divisor zero, output error waveform displayed in simulation. here code:

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;  entity division_in     port ( : in  std_logic_vector (7 downto 0);            b : in  std_logic_vector (7 downto 0);            clk : in  std_logic;            y : out  std_logic_vector (7 downto 0);            err : out  std_logic); end division_in;  architecture behavioral of division_in  begin    process(clk)   begin     if clk='1' , clk'event -- error here       y <= conv_std_logic_vector(conv_integer(a)/conv_integer(b),8);       err <= '0';     elsif b = 0       err <= '1';     end if;   end process;  end behavioral; 

when try use "check syntax" in xilinx ise 9.1i (which used university), there no syntax errors displayed on transcript. use testbench waveform simulate no problems. however, when import code quartus ii, got 5 errors in message in one:

error (10818): can't infer register "err" @ division_in.vhd(45) because not hold value outside clock edge

i don't know i've done wrong in copying exact code xilinx quartus little appreciated on why got error on quartus ii not on xilinx ise 9.1i. since xilinx ise not compatible laptop anymore, use quartus ii instead since has simulation feature "vector waveform file" simulation.

ok, first thing's first, not use ieee.std_logic_arith.all; or use ieee.std_logic_unsigned.all. should use ieee.numeric_std.all, gives arithmetic using types signed , unsigned, along casts , conversion functions std_logic_vector , integer.

now let's @ code:

if clk='1' , clk'event -- error here   y <= conv_std_logic_vector(conv_integer(a)/conv_integer(b),8);   err <= '0'; elsif b = 0   err <= '1'; end if; 

looking @ err signal only, says on rising clock edge, set err '0', otherwise if b = 0, set err '1'. mentioned works in simulation, synthesis need think means in real hardware. how imagine case there isn't clock edge being detected? answer cannot.

it's not clear you're trying achieve, 2 alternatives work, having made package changes above, are:

if rising_edge(clk) -- use rising_edge() function   y <= std_logic_vector(signed(a)/signed(b));   err <= '0'; -- synchronous clear of `err` end if; if signed(b) = 0 -- asynchronous set of `err`   err <= '1'; end if; 

or

if rising_edge(clk)   y <= std_logic_vector(signed(a)/signed(b));   if signed(b) = 0     err <= '1'; -- synchronous control of `err`   else     err <= '0';   end if; end if; 

the code need less type casts if gave ports types are, i.e. signed. core of process this:

if rising_edge(clk)   y <= / b;   if b = 0     err <= '1'; -- synchronous control of `err`   else     err <= '0';   end if; end if; 

i hope can see how easier read.