swift - FBSimulatorControl : Convert CVPixelBufferRef data to jpeg data for streaming -


i developing cli in swift , using fbsimulatorcontrol in it. want stream data obtained consumedata: delegate method. per data obtained in method data obtained cvpixelbufferref

i logged issue in github repo of fbsimulatorcontrol.

i tried regenerate cvpixelbuffer data , tried obtain ciimage , convert jpeg data. not seem work. can me this? adding below code i've tried

var pixelbuffer:cvpixelbuffer? = nil let result = cvpixelbuffercreate(kcfallocatordefault, 750, 1334, kcvpixelformattype_32bgra, nil, &pixelbuffer)  if result != kcvreturnsuccess {     print("pixel buffer create success")     return } cvpixelbufferlockbaseaddress(pixelbuffer!, .init(rawvalue: 0)) let ydestplane:unsafemutablerawpointer? = cvpixelbuffergetbaseaddressofplane(pixelbuffer!, 0)  if ydestplane == nil {     print("failed create ydestplane")     return }  let nsdata = data nsdata let rawptr = nsdata.bytes  memcpy(ydestplane!, rawptr, 750*1334*4)  cvpixelbufferunlockbaseaddress(pixelbuffer!, .init(rawvalue: 0)) kcvpixelformattype_32bgra, getbasea, 2208, null, null, nil, &pixelbuffer)  if #available(osx 10.12, *) {     let ciimage = ciimage.init(cvpixelbuffer: pixelbuffer!)     let tempcontext = cicontext.init(options: nil)     let videoimage = tempcontext.createcgimage(ciimage, from: cgrect.init(x: 0, y: 0, width: cvpixelbuffergetwidth(pixelbuffer!), height: cvpixelbuffergetheight(pixelbuffer!)))     let imagesize: nssize = nsmakesize(750, 1334)     let nsimagetest = nsimage(cgimage: videoimage!, size: imagesize)     if let bits = nsimagetest.representations.first as? nsbitmapimagerep {         let jpegfinaldata = bits.representation(using: .jpeg, properties: [:])         if self.isstreaming {             var simindex:int?             in 0...(auconnectionsimulatormap.instance.simconnectionmap.count-1) {                 if sim.udid == auconnectionsimulatormap.instance.simconnectionmap[i].sim.sim.udid {                     simindex =                     break                 }             }             var finaldata:data = data()             let finaldict = ["data":["type":"onscreenframe","value":jpegfinaldata!]] dictionary<string,any>             try! finaldata.pack(finaldict)             auconnectionsimulatormap.instance.simconnectionmap[simindex!].ws?.write(data: finaldata)         }      }  } else {     // fallback on earlier versions }


Comments

Post a Comment

Popular posts from this blog

Is there a better way to structure post methods in Class Based Views -

i'm using class based views in django , never specify url in ajax calls , omit action parameter in form because know these requests go through post method of class based view. notice view - profile page make many requests depending on user updating on page - post method become convoluted , if/else mess example: def post(self, request, *args, **kwargs): # handle user changing available date if request.post.get('availabledate') != none: self.updateavailabledate(request) return jsonresponse({'result':'success'}) if request.post.get('newprojectname') != none: creative_user = creativeuserprofile.objects.get(id = request.user.id) project = project.create_project(creative_user, request.post['newprojectname']) project.save() return jsonresponse({'projectid': project.id }) if request.post.get('projectimage') != none , request.files['file']: proj...
Read more

performance - Why is XCHG reg, reg a 3 micro-op instruction on modern Intel architectures? -

i'm doing micro-optimization on performance critical part of code , came across sequence of instructions (in at&t syntax): add %rax, %rbx mov %rdx, %rax mov %rbx, %rdx i thought had use case xchg allow me shave instruction , write: add %rbx, %rax xchg %rax, %rdx however, dimay found agner fog's instruction tables , xchg 3 micro-op instruction 2 cycle latency on sandy bridge, ivy bridge, broadwell, haswell , skylake. 3 whole micro-ops , 2 cycles of latency! 3 micro-ops throws off 4-1-1-1 cadence , 2 cycle latency makes worse original in best case since last 2 instructions in original might execute in parallel. now... cpu might breaking instruction micro-ops equivalent to: mov %rax, %tmp mov %rdx, %rax mov %tmp, %rdx where tmp anonymous internal register , suppose last 2 micro-ops run in parallel latency 2 cycles. given register renaming occurs on these micro-architectures, though, doesn't make sense me done way. why wouldn't register renamer ...
Read more

c# - Asp.net web api : redirect unauthorized requst to forbidden page -

im trying redirect unauthorized request forbidden page instead i'm getting forbidden page in response body , how can fix ? here's startup class : app.createperowincontext(storecontext.create); app.createperowincontext<applicationusermanager>(applicationusermanager.create); app.createperowincontext<applicationsigninmanager>(applicationsigninmanager.create); app.usecookieauthentication(new cookieauthenticationoptions { authenticationtype = defaultauthenticationtypes.applicationcookie, expiretimespan = timespan.fromdays(30), }); app.useexternalsignincookie(defaultauthenticationtypes.externalcookie); app.usetwofactorsignincookie(defaultauthenticationtypes.twofactorcookie, timespan.fromminutes(5)); app.usetwofactorrememberbrowsercookie(defaultauthenticationtypes.twofactorrememberbrowsercookie); the method im trying reach : [httpget] [authorize(roles = "admin")] public string getcurrentusername() { return userman...
Read more