Turning an ALU 1-bit into ALU 8-bit in Verilog -


below 1-bit alu proven work. use 1-bit alu 8-bit alu , needs pass test bench. far compiled 8-bit alu code doesn't seem work. help?

module aluslice(a,b,ci,m,s,f,co); //code 1-bit input a,b,ci,m,s; output f,co; wire [3:0] tf; wire [3:0] tc;  fulladder f1(tf[3],tc[3],a,b,ci); assign tf[0] = & b; assign tf[1] = | b; assign tf[2] = ~a;  assign tc[2:0] = 0; dual4to1mux mux1(f,co,{m,s},tf,tc); endmodule     module alu8bit(s1,s0, a, b, carryin, carryout, f);//what have far input [7:0] a,b; input s1,s0,carryin; output [7:0] f; output carryout;  wire [7:0] c;  aluslice a0(f[0],c[0],a[0],b[0],carryin,s0,s1); aluslice a1(f[1],c[1],a[1],b[1],c[0],s0,s1); aluslice a2(f[2],c[2],a[2],b[2],c[1],s0,s1); aluslice a3(f[3],c[3],a[3],b[3],c[2],s0,s1); aluslice a4(f[4],c[4],a[4],b[4],c[3],s0,s1); aluslice a5(f[5],c[5],a[5],b[5],c[4],s0,s1); aluslice a6(f[6],c[6],a[6],b[6],c[5],s0,s1); aluslice a7(f[7],carryout,a[7],b[7],c[6],s0,s1);  endmodule

without more complete picture of everything, not easy tell if issue. 1 reason might failing seems did not hook aluslice modules correctly in alubit. port (io) order of aluslice module should inputs followed outputs, have outputs followed inputs in instantiations. best way void these kinds of bugs explicitly connect ports respective lines rather relying on order, so:

aluslice a0(.a(a[0]), .b(b[0]), .ci(carryin), .m(s1), .s(s0), .f(f[0]), .co(c[0]));

this way, connected intend (ie, a[0] connected a input, b[0] b, carryin ci, etc) without making mistakes order, or when add new ports or take away, still hooked expected.


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