machine learning - Word embedding training -


i have 1 corpus word embedding. using corpus, trained word embedding. however, whenever train word embedding, results quite different(this results based on k-nearest neighbor(knn)). example, in first training, 'computer' nearest neighbor words 'laptops', 'computerized' ,'hardware'. but, in second training, knn words 'software', 'machine',...('laptops' low ranked!) - training performed independently 20 epochs, , hyper-parameters same.

i want train word embedding similar(e.g., 'laptops' high ranked). how should do? should modulate hyper-parameters(learning rate, initializing, etc)?

you didn't word2vec software you're using, might change relevant factors.

the word2vec algorithm inherently uses randomness, in both initialization , several aspects of training (like selection of negative-examples, if using negative-sampling, or random downsampling of very-frequent words). additionally, if you're doing multithreaded training, essentially-random jitter in os thread scheduling change order of training examples, introducing source of randomness. shouldn't expect subsequent runs, exact same parameters , corpus, give identical results.

still, enough data, suitable parameters, , proper training loop, relative-neighbors results should similar run-to-run. if it's not, more data or more iterations might help.

wildly-different results if model overlarge (too many dimensions/words) corpus – , prone overfitting. is, finds great configuration data, through memorizing idiosyncracies, without achieving generalization power. , if such overfitting possible, there typically many equally-good such memorizations – can different run-to-tun. meanwhile, right-sized model lots of data instead capturing true generalities, , those more consistent run-to-run, despite randomization.

getting more data, using smaller vectors, using more training passes, or upping minimum-count of word-occurrences retain/train word might help. (very-infrequent words don't high-quality vectors, wind interfering quality of other words, , randomly intruding in most-similar lists.)

to know else might awry, should clarify in question things like:

  • software used
  • modes/metaparameters used
  • corpus size, in number of examples, average example size in words, , unique-words count (both in raw corpus, , after minumum-count applied)
  • methods of preprocessing
  • code you're using training (if you're managing multiple training-passes yourself)

Comments

Post a Comment

Popular posts from this blog

Is there a better way to structure post methods in Class Based Views -

i'm using class based views in django , never specify url in ajax calls , omit action parameter in form because know these requests go through post method of class based view. notice view - profile page make many requests depending on user updating on page - post method become convoluted , if/else mess example: def post(self, request, *args, **kwargs): # handle user changing available date if request.post.get('availabledate') != none: self.updateavailabledate(request) return jsonresponse({'result':'success'}) if request.post.get('newprojectname') != none: creative_user = creativeuserprofile.objects.get(id = request.user.id) project = project.create_project(creative_user, request.post['newprojectname']) project.save() return jsonresponse({'projectid': project.id }) if request.post.get('projectimage') != none , request.files['file']: proj...
Read more

performance - Why is XCHG reg, reg a 3 micro-op instruction on modern Intel architectures? -

i'm doing micro-optimization on performance critical part of code , came across sequence of instructions (in at&t syntax): add %rax, %rbx mov %rdx, %rax mov %rbx, %rdx i thought had use case xchg allow me shave instruction , write: add %rbx, %rax xchg %rax, %rdx however, dimay found agner fog's instruction tables , xchg 3 micro-op instruction 2 cycle latency on sandy bridge, ivy bridge, broadwell, haswell , skylake. 3 whole micro-ops , 2 cycles of latency! 3 micro-ops throws off 4-1-1-1 cadence , 2 cycle latency makes worse original in best case since last 2 instructions in original might execute in parallel. now... cpu might breaking instruction micro-ops equivalent to: mov %rax, %tmp mov %rdx, %rax mov %tmp, %rdx where tmp anonymous internal register , suppose last 2 micro-ops run in parallel latency 2 cycles. given register renaming occurs on these micro-architectures, though, doesn't make sense me done way. why wouldn't register renamer ...
Read more

c# - Asp.net web api : redirect unauthorized requst to forbidden page -

im trying redirect unauthorized request forbidden page instead i'm getting forbidden page in response body , how can fix ? here's startup class : app.createperowincontext(storecontext.create); app.createperowincontext<applicationusermanager>(applicationusermanager.create); app.createperowincontext<applicationsigninmanager>(applicationsigninmanager.create); app.usecookieauthentication(new cookieauthenticationoptions { authenticationtype = defaultauthenticationtypes.applicationcookie, expiretimespan = timespan.fromdays(30), }); app.useexternalsignincookie(defaultauthenticationtypes.externalcookie); app.usetwofactorsignincookie(defaultauthenticationtypes.twofactorcookie, timespan.fromminutes(5)); app.usetwofactorrememberbrowsercookie(defaultauthenticationtypes.twofactorrememberbrowsercookie); the method im trying reach : [httpget] [authorize(roles = "admin")] public string getcurrentusername() { return userman...
Read more